MM58274C Timing Circuits => Real Time Clocks

MM58274C Timing Circuits => Real Time Clocks

Features, Applications

The MM58274C is fabricated using low threshold metal gate CMOS technology and is designed to operate in bus oriented microprocessor systems where a real time clock and calendar function are required The on-chip 32 768 kHz crystal controlled oscillator will maintain timekeeping down 2V to allow low power standby battery operation This device is pin compatible with the MM58174A but continues timekeeping up to tens of years The is a direct replacement for the MM58274 offering improved Bus access cycle times

Features
Applications
Point of sale terminals Teller terminals Word processors Data logging Industrial process control

Same pin-out MM58174A MM58274B and MM58274 Timekeeping from tenths of seconds to tens of years in independently accessible registers Leap year register Hours counter programmable for or 24-hour operation Buffered crystal frequency output in test mode for easy oscillator setting Data-changed flag allows simple testing for time rollover Independent interrupting time with open drain output Fully TTL compatible Low power standby operation 2 2V) Low cost 16-pin DIP and 20-pin PCC

TRI-STATE is a registered trademark of National Semiconductor Corp MicrobusTM is a trademark of National Semiconductor Corp C1995 National Semiconductor Corporation

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications DC Input or Output Voltage DC Input or Output Diode Current Storage Temperature TSTG Supply Voltage VDD Power Dissipation PD Lead Temperature (Soldering 10 seconds)

Operating Supply Voltage Standby Mode Supply Voltage DC Input or Output Voltage Operating Temperature Range Min b 40 Max 55 VDD 85 Units

Symbol VIH Parameter High Level Input Voltage (except XTAL IN) Low Level Input Voltage (except XTAL IN) High Level Output Voltage (DB0­DB3) High Level Output Voltage (INT) Low Level Output Voltage (DB0­DB3 INT) Low Level Input Current (AD0­AD3 DB0­DB3) Low Level Input Current (WR RD) Low Level Input Current (CS) Ouput High Level Leakage Current (INT) Average Supply Current IOH b20 mA IOH 6 mA IOH b20 mA (In Test Mode) IOL 20 mA iOL 6 mA

VIN e VSS (Note 2) VIN e VSS (Note 2) VIN e VSS (Note 2) VOUT e VDD All VIN e VCC or Open Circuit VDD 2 2V (Standby Mode) VDD 5 0V (Active Mode)

Input Capacitance Output Capacitance (Outputs Disabled)

Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur All voltages referenced to ground unless otherwise noted Note 2 The DB0­DB3 and AD0­AD3 lines all have active P-channel pull-up transistors which will source current The CS RD and WR lines have internal pull-up resistors to VDD

READ TIMING DATA FROM PERIPHERAL TO MICROPROCESSOR VDD 100 pF Commercial Specification 85 C Min tAD tCSD tRD tRW tRA tCSH tRH tHZ Address Bus Valid to Data Valid Chip Select On to Data Valid Read Strobe On to Data Valid Read Strobe Width (Note 3 Note 7) Address Bus Hold Time from Trailing Edge of Read Strobe Chip Select Hold Time from Trailing Edge of Read Strobe Data Hold Time from Trailing Edge of Read Strobe Time from Trailing Edge of Read Strobe Until O P Drivers are TRI-STATE Typ 390 140 Max DC ns

WRITE TIMING DATA FROM MICROPROCESSOR TO PERIPHERAL VDD 0 5V Commercial Specification 85 C Min tAW tCSW tDW tWW tWCS tWA tWD tAWS Address Bus Valid to Write Strobe O (Note 4 Note 6) Chip Select On to Write Strobe O Data Bus Valid to Write Strobe O Write Strobe Width (Note 6) Chip Select Hold Time Following Write Strobe O Address Bus Hold Time Following Write Strobe O Data Bus Hold Time Following Write Strobe O Address Bus Valid Before Start of Write Strobe Typ Max ns

1. Note 3 Except for special case restriction with interrupts programmed max read strobe width of control register (ADDR 30 ms See section on Interrupt Programming Note 4 All timings measured to the trailing edge of write strobe (data latched by the trailing edge of WR) Note 5 Input test waveform peak voltages are 2 4V and 0 4V Output signals are measured to their 2 4V and 0 4V levels Note 6 Write strobe as used in the Write Timing Table is defined as the period when both chip select and write inputs are low a WR Hence write strobe commences when both signals are low and terminates when the first signal returns high Note 7 Read strobe as used in the Read Timing Table is defined as the period when both chip select and read inputs are low a RD Note 8 Typical numbers are at VCC 5 0V and 25 C